Pci Express Root Complex Drivers
Lattice’s PCI Express Root Complex (RC) Lite core provides an x1 or x4 root complex solution from the electrical SERDES interface, physical layer, data link layer and a minimum transaction layer in PCI express protocol stack. This IP is a lighter version of the root complex intended to use in simple bridging application to local bus. Apr 13, 2020 2nd Generation Intel Core Processor Family PCI Express Controller - 0101 Intel 6 series/C206 Series Chipset Family PCI Express Root Port 1 - 1C10 Devices plugged into the computer are a USB mouse, USB keyboard, and LAN. The only other thing plugged in is the monitor, so this is a very basic setup.
Introduction
The PCI Express (PCIe) module is a multi-lane I/O interconnect providinglow pin count, high reliability, and high-speed data transfer at ratesof up to 8.0 Gbps per lane per direction. It is a 3rd Generation I/O Interconnecttechnology succeeding ISA and PCI bus that is designed to be used as ageneral-purpose serial I/O interconnect in multiple market segments,including desktop, mobile, server, storage and embedded communications.
Features of J7ES
There are four instances of the PCIe subsystem. Following are some of themain features:
- Each instance can be configured to operate in Root Complex mode orEnd Point mode
- One or two lane configuration, capable up to 8.0 Gbps/lane (Gen3)
- Support for Legacy, MSI and MSI-X Interrupt
- There can be 32 different address mappings in outbound address translationunit. The mappings can be from regions reserved for each PCIe instance.
- For instance PCIE0 and PCIE1, there are two regions in SoC Memory Map:
- 128 MB region with address in lower 32 bits
- 4 GB region with address above 32 bits
- For instance PCIE2 and PCIE3, there are two regions in SoC Memory Map:
- 128 MB region with address above 32 bits
- 4 GB region with address above 32 bits
- For instance PCIE0 and PCIE1, there are two regions in SoC Memory Map:
Capabilities of J721E EVM
There are three instances of the PCIe subsystem on the EVM. Following aresome of the details for each instance:
| Instance | Supported lanes | Supported Connector |
|---|---|---|
| PCIE0 | 1 lane | Standard female connector |
| PCIE1 | 2 lane | Standard female connector |
| PCIE2 | 2 lane | m.2 connector keyed for SSD (M key) |
Hardware Setup Details
J721E is, by default, intended to be operated inRoot Complex mode.
For End Point mode, PCIE_1L_MODE_SEL (switch 5) and PCIE_2L_MODE_SEL (switch 6)should be set to ‘0’.
RC Software Architecture
Following is the software architecture for Root Complex mode:
Following is a brief explanation of layers shown in the diagram:
- There are different drivers for the connected PCIe devices likepci_endpoint_test, tg-3, r8169, xhci-pci, ahci, etc. It could bevendor-specific like most of the ethernet cards (tg3, r8169) or class-specificlike xhci-pci and ahci. Each of these drivers will also interact with it’s owndomain-specific stack. For example, tg3 will interface with network stack, andxhci-pci will interface with USB stack.
- The PCI core layer scans the PCIe bus to identify and detect any PCIe devices.It also binds the driver from the layer above, for the PCIe device, based onvendorid, deviceid and class.
- The PCI BIOS layer handles resource management. For example, allocation ofmemory resources for BARs.
- The bottom-most layer consists of the PCIe platform drivers like pcie-cadence,pcie-designware, etc. pci-j721e and pci-dra7xx are TI’s wrappers over thesedrivers. They configure platform-specific controllers and performactual register writes.
RC Device Configuration
DTS Modification
The default dts for J721E is configured to be used inroot complex mode.
Linux Driver Configuration
The following config options have to be enabled in order to configure thePCI controller to be used in Root Complex mode.
Testing Details
The RC should enumerate any off-the-shelf PCIe cards. It has been testedwith Ethernet cards, NVMe cards, PCIe USB card, PCIe WiFi card, PCIe SATAcard and also to J721E in loopback mode.
In order to see if the connected card is detected, lspci utility should beused. Different utilities can be used depending on the cards.
Following are the outputs for some of them:
Loopback mode (J721E EVM to J721E EVM)
Two J721E EVMs can be connected in loopback mode by following the stepsexplained inEnd Point (EP) Device Configurationsection for End Point (EP) andHOST Device Configurationsection for Root Complex (RC) inPCIe End Point documentation. The pci-epf-testdriver will be configured for End Point(EP) using those steps.
The lspci output on the Root Complex (RC) device is as follows:
WiFi card
- lspci output
- Test using ping
NVMe SSD
- lspci output
- Test using hdparm
- Test using dd
J7200 Testing Details
PCIe and QSGMII uses the same SERDES in J7200. The default SDK is enabled for QSGMII. In order totest PCIe, Ethfw firmware shouldn’t be loaded and PCIe overlay file should be applied.
The simplest way to avoid ethfw from being loaded is to link j7200-main-r5f0_0-fw to IPC firmware.
The following Device Tree Overlay should be applied for testing J7200 RC.
The following command should be given in u-boot to apply overlay
Introduction
The PCI Express (PCIe) module is a multi-lane I/O interconnect providinglow pin count, high reliability, and high-speed data transfer at ratesof up to 8.0 Gbps per lane per direction. It is a 3rd Generation I/O Interconnecttechnology succeeding ISA and PCI bus that is designed to be used as ageneral-purpose serial I/O interconnect in multiple market segments,including desktop, mobile, server, storage and embedded communications.
Features of J7ES
There are four instances of the PCIe subsystem. Following are some of themain features:
- Each instance can be configured to operate in Root Complex mode orEnd Point mode
- One or two lane configuration, capable up to 8.0 Gbps/lane (Gen3)
- Support for Legacy, MSI and MSI-X Interrupt
- There can be 32 different address mappings in outbound address translationunit. The mappings can be from regions reserved for each PCIe instance.
- For instance PCIE0 and PCIE1, there are two regions in SoC Memory Map:
- 128 MB region with address in lower 32 bits
- 4 GB region with address above 32 bits
- For instance PCIE2 and PCIE3, there are two regions in SoC Memory Map:
- 128 MB region with address above 32 bits
- 4 GB region with address above 32 bits
- For instance PCIE0 and PCIE1, there are two regions in SoC Memory Map:
Capabilities of J721E EVM
There are three instances of the PCIe subsystem on the EVM. Following aresome of the details for each instance:
| Instance | Supported lanes | Supported Connector |
|---|---|---|
| PCIE0 | 1 lane | Standard female connector |
| PCIE1 | 2 lane | Standard female connector |
| PCIE2 | 2 lane | m.2 connector keyed for SSD (M key) |
Hardware Setup Details
J721E is, by default, intended to be operated inRoot Complex mode.
For End Point mode, PCIE_1L_MODE_SEL (switch 5) and PCIE_2L_MODE_SEL (switch 6)should be set to ‘0’.
RC Software Architecture
Following is the software architecture for Root Complex mode:
Following is a brief explanation of layers shown in the diagram:
- There are different drivers for the connected PCIe devices likepci_endpoint_test, tg-3, r8169, xhci-pci, ahci, etc. It could bevendor-specific like most of the ethernet cards (tg3, r8169) or class-specificlike xhci-pci and ahci. Each of these drivers will also interact with it’s owndomain-specific stack. For example, tg3 will interface with network stack, andxhci-pci will interface with USB stack.
- The PCI core layer scans the PCIe bus to identify and detect any PCIe devices.It also binds the driver from the layer above, for the PCIe device, based onvendorid, deviceid and class.
- The PCI BIOS layer handles resource management. For example, allocation ofmemory resources for BARs.
- The bottom-most layer consists of the PCIe platform drivers like pcie-cadence,pcie-designware, etc. pci-j721e and pci-dra7xx are TI’s wrappers over thesedrivers. They configure platform-specific controllers and performactual register writes.
RC Device Configuration
DTS Modification
The default dts for J721E is configured to be used inroot complex mode.
Linux Driver Configuration
The following config options have to be enabled in order to configure thePCI controller to be used in Root Complex mode.
Pci Express Root Complex Definition
Testing Details
Pci Express Root Complex Driver Windows 10 Download
The RC should enumerate any off-the-shelf PCIe cards. It has been testedwith Ethernet cards, NVMe cards, PCIe USB card, PCIe WiFi card, PCIe SATAcard and also to J721E in loopback mode.
In order to see if the connected card is detected, lspci utility should beused. Different utilities can be used depending on the cards.
Following are the outputs for some of them:
What Is Pci Express Root Complex
Loopback mode (J721E EVM to J721E EVM)
Two J721E EVMs can be connected in loopback mode by following the stepsexplained inEnd Point (EP) Device Configurationsection for End Point (EP) andHOST Device Configurationsection for Root Complex (RC) inPCIe End Point documentation. The pci-epf-testdriver will be configured for End Point(EP) using those steps.
The lspci output on the Root Complex (RC) device is as follows:
WiFi card
- lspci output
- Test using ping
NVMe SSD
- lspci output
- Test using hdparm
- Test using dd
J7200 Testing Details
PCIe and QSGMII uses the same SERDES in J7200. The default SDK is enabled for QSGMII. In order totest PCIe, Ethfw firmware shouldn’t be loaded and PCIe overlay file should be applied.
The simplest way to avoid ethfw from being loaded is to link j7200-main-r5f0_0-fw to IPC firmware.
The following Device Tree Overlay should be applied for testing J7200 RC.
Pci Express Root Complex Download
The following command should be given in u-boot to apply overlay